A 249-Mpixel/s HEVC Video-Decoder Chip for 4K Ultra-HD Applications
Abstract
High Efficiency Video Coding, the latest video standard, uses larger and variable-sized coding units and longer interpolation filters than H.264/AVC to better exploit redundancy in video signals. These algorithmic techniques enable a 50% decrease in bitrate at the cost of computational complexity, external memory bandwidth, and, for ASIC implementations, on-chip SRAM of the video codec. This paper describes architectural optimizations for an HEVC video decoder chip. The chip uses a two-stage subpipelining scheme to reduce on-chip SRAM by 56∼kbytes—a 32% reduction. A high-throughput read-only cache combined with DRAM-latency-aware memory mapping reduces DRAM bandwidth by 67%. The chip is built for HEVC Working Draft 4 Low Complexity configuration and occupies 1.77
- Publication:
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IEEE Journal of Solid-State Circuits
- Pub Date:
- January 2014
- DOI:
- Bibcode:
- 2014IJSSC..49...61T
- Keywords:
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- DRAM bandwidth reduction;
- entropy decoder;
- high —efficiency video coding;
- inverse discrete cosine transform (IDCT);
- motion compensation cache;
- ultrahigh definition (ultra HD);
- video-decoder chip
